Nonvolatile memory circuit for recording multiple bit information

ABSTRACT

The present invention provides a multi-bits non-volatile memory circuit having a cell transistor with non-conductive trap gate which has a cell array capable of reading a plural data simultaneously. The present invention is a non-volatile memory circuit in which a plurality of cell transistors M having a non-conductive trapping gate TG are arranged, comprising: a plurality of source-drain lines SDL, which are connected commonly with the source-drain regions SD 1,  SD 2  of cell transistors adjacent in row direction, wherein these adjacent source-drain lines are set to a floating state F, a read-out voltage application state BL, a reference voltage state OV, a read-out voltage state BL, and a floating state F, and the source-drain lines SDL in the read-out voltage state is caused to function as bit lines, such that a plurality of data are read out simultaneously. The above states are generated by the page buffer P/B connected to the source-drain line. The data read and hold are performed by the page buffer.

TECHNICAL FIELD

The present invention relates to a non-volatile memory circuitconstituted by cell transistors which have a non-conductive trappinggate and which are capable of storing multiple bit data, and, moreparticularly, to a non-volatile memory circuit which has a cell arrayconstitution capable of simultaneously reading out stored data from amultiplicity of cell transistors.

TECHNICAL BACKGROUND

Non-volatile memories that utilize semiconductors are widely used asinformation recording media because such non-volatile memories arecapable of holding information even if the power supply is OFF, and ofhigh speed read-out. In recent years, non-volatile memories have beenutilized in mobile information terminals, and utilized as recordingmedia for digital cameras and for digital music in the form of MP3 data,for example.

Non-volatile memories, such as the flash memories that are currently inwidespread use, are constructed having, on a channel region between asource region and drain region, a conductive floating gate and a controlgate. A non-volatile memory of this kind is constituted such that afloating gate is buried in a gate insulating film, and one-bitinformation is stored according to whether charge is or is not injectedinto this floating gate. Due to the fact that the floating gate of suchwidely used non-volatile memories is conductive, when defects, howeversmall, are present in the gate oxide film, electrons in the floatinggate are all lost via these defects and there is a problem in that highreliability is unattainable.

Other than the widely used non-volatile memories mentioned above, a newtype of non-volatile memory has been proposed that is provided with anon-conductive charge trapping gate in place of a floating gate, andthat stores two-bit information by causing charge to be trapped locallyat the source side and the drain side of the trapping gate. For example,a non-volatile memory of this kind is disclosed in the PCT applicationWO99/07000 “Two Bit Non-Volatile Electrically Erasable and ProgrammableSemiconductor Memory Cell Utilizing Asymmetrical Charge Trapping”. Sincethe trapping gate of this non-volatile memory is non-conductive, theprobability of electrons injected locally being lost is low, and it isthus possible to make reliability high.

FIG. 1 is a figure to show the constitution of a cell transistor of theabove-mentioned conventional two-bit non-volatile memory. (1) of FIG. 1is a cross-sectional view thereof, and (2) of FIG. 1 is an equivalentcircuit diagram thereof. Source-drain regions SD1, SD2 are formed at thesurface of a silicon substrate 1, and a trapping gate TG formed from asilicon nitride film or the like, and a control gate CG of a conductivematerial, are formed on a channel region. The trapping gate TG is buriedin an insulating film 2 made of silicon oxide film or the like such thatthe whole body is a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor)structure. By utilizing the difference in the bandgaps of the siliconnitride film and the silicon oxide film, it is possible to cause chargeto be trapped and held in the silicon nitride film.

One feature of the non-volatile memory is that the trapping gate TG isconstituted from a non-conductive substance such as an insulating body,or a dielectric body, and, in a case in which charge is injected intothis trapping gate TG, charge within the trapping gate is unable tomove. As a result, it is possible to make a distinction between a casein which charge is injected in the vicinity of a first source-drainregion SD1, and a case in which charge is injected in the vicinity of asecond source-drain region SD2, and it is thus possible to recordtwo-bit data.

(2) of FIG. 1 is an equivalent circuit diagram of the above-mentionedtwo-bit non-volatile memory. Since the trapping gate TG isnon-conductive, this trapping gate TG is equivalent to a constitution inwhich separate MOS transistors are respectively formed in a firsttrapping gate region TSD1 in the vicinity of the first source-drainregion SD1, and in a second trapping gate region TSD2 in the vicinity ofthe second source-drain region SD2. Further, in the course of theabove-described read-out and programming (write) operations, the firstand second source-drain regions SD1, SD2 are utilized either as sourceregions or drain regions, and these source or drain regions SD1, SD2 aretherefore referred to, in this specification, as the first source-drainregion SD1 and the second source-drain region SD2, respectively.

FIG. 2 is a figure to illustrate programming, erasure and read-out of aconventional two-bit non-volatile memory. The voltage applied to thefirst source-drain region SD1 is termed V(SD1), the voltage applied tothe second source-drain region SD2 is termed V(SD2), and the voltageapplied to the control gate CG is termed Vg.

As shown in (1) of FIG. 2, the programming (write) of the non-volatilestorage memory is executed by applying voltages Vg=10V, V(SD1)=0V,V(SD2)=6V, for example, and by thus injecting hot electrons produced inthe vicinity of the second source-drain region SD2 into the secondtrapping gate region TSD2 close to the second source-drain region SD2.

In addition, in the course of an erase operation, as shown in (2) FIG.2, Vg=−5V is applied to the control gate CG, and 5V is applied to thefirst or second source-drain region SD1 or SD2, or to both of them, toextract electrons from the trapping gate TG by utilizing the FN tunneleffect (the Fowler-Nordheim Tunnel effect). As a result of injection, atthe same time, of hot holes produced in the vicinity of the source-drainregions SD1, SD2, into the trapping gate TG, the charge is neutralizedwithin the trapping gate TG.

Next, with regard to read-out, a voltage, whose bias is the reverse ofthe voltage of the programming operation, is applied between the firstand second source-drain regions SD1, SD2, to detect whether or notelectrons are trapped in the second trapping gate region TSD2. In otherwords, in order to read out the state of the second trapping gate regionTSD2, voltages applied are Vg=3V, V(SD1)=1.6V, V(SD2)=0V, for example.Here, as shown in (3) of FIG. 2, when electrons are present in thesecond trapping gate region TSD2 in the vicinity of the secondsource-drain region SD2, the channel below the gate does not extend soas to touch the second source-drain region SD2, and, consequently, achannel current does not flow (0 data storage state). Conversely, asshown in (4) of FIG. 2, when electrons are not present in the secondtrapping gate region TSD2 in the vicinity of the second source-drainregion SD2, the channel reaches as far as the second source-drain regionSD2, and, consequently, a channel current flows (1 data storage state).It is thus possible to detect whether or not electrons have accumulatedin the second trapping gate region TSD2, and to detect the ON and OFF ofa cell transistor, that is, the existence of a current.

Furthermore, in read-out of the non-volatile storage memory, when, asshown in (5) of FIG. 2, voltages applied are: Vg=3V, V(SD1)=0V,V(SD2)=1.6V, i.e. when the voltage application state between the firstand second source-drain regions is the reverse of that in (3) of FIG. 2mentioned above, even if electrons are, for example, present in thesecond trapping gate region TSD2, the state is the same as a MOStransistor whose channel is pinched off, and, as a result of anexpanding depletion layer between the second source-drain region and thesubstrate, a channel current flows. Therefore, in a voltage applicationstate of this kind, it is possible to detect whether or not electronshave accumulated in the first trapping gate region TSD1 in the vicinityof the first source-drain region SD1, irrespective of the existence ofelectrons in the second trapping gate region TSD2.

As described above, a conventional memory is capable of recordingtwo-bit information by means of the accumulation or non-accumulation ofelectrons in the nitride film region TSD1 in the vicinity of the firstsource-drain region SD1 and in the nitride film region TSD2 in thevicinity of the second source-drain region SD2, and is thereforeadvantageous with respect to a larger capacity and a cost reduction perchip as a result of a reduced chip surface area.

FIG. 3 is a figure to show a state in which two-bit information isrecorded in the above-mentioned non-volatile memory. In the figure,black spots represent electrons. (1) of FIG. 3 shows a state data=11 inwhich electrons are not captured in either of the first or secondtrapping gate regions TSD1, TSD2. (2) of FIG. 3 shows a state data=01 inwhich electrons are captured in the second trapping gate region TSD2.(3) of FIG. 3 shows a state data=00 in which electrons are captured inthe first and second trapping gate regions TSD1, TSD2. Further, (4) ofFIG. 3 shows a state data=10 in which electrons are captured in thefirst trapping gate region TSD1.

FIG. 4 is a figure to show the constitution of a conventional memorycell array. As described hereinabove, a non-volatile memory with atwo-bit recording capability applies voltages from one source-drainregion of a cell transistor to the other source-drain region thereof toperform a desired data read-out. Therefore, such a non-volatile memoryis capable of applying voltages in both directions to the same celltransistor, and there is thus a requirement to perform the read-out ofdata from each of two source-drain lines SDL that are connected with asource-drain region on both sides.

According to the conventional example shown in FIG. 4, four word linesWL0 to WL3, and cell transistors M1 to M8 whose control gates are eachconnected with these word lines, are provided. Further, for a largecapacity, the source-drain regions of adjacent cell transistors areshared and common source-drain lines SDL0 to SDL7 are connected. Inaddition, for every four cell transistors, one pair of column lines L1,L2 and L3, L4, and four selective transistors Q1 to Q4 of one set, whichconnect these column lines and source-drain lines SDL0 to SDL7, areprovided. In response to select signals SEL1 to SEL4, any of selectivetransistors Q1 to Q4 are conductive such that column lines L1 to L4 aresuitably connected with source-drain lines.

FIG. 5 is a chart to illustrate the operation of FIG. 4. When celltransistor M1 is selected, as shown in FIG. 5, select signals SEL1 andSEL3 are at an L level such that transistors Q1, Q3 are non-conductive,and select signals SEL2, SEL4 are at an H level such that transistorsQ2, Q4 are conductive. As a result, the source-drain lines SDL0, SDL1 ofthe cell transistor M1 are respectively connected with the column linesL1, L2. Therefore, when 0V is applied to column line L2 and apredetermined read-out voltage (1.6V) is applied for a bit line tocolumn line L1, a voltage is applied to cell transistor M1 from the leftside to the right side thereof, and it is possible to detect whether ornot a current is flowing in column line L1 by means of a sense ampcircuit (not shown).

At this time, the source-drain lines SDL4, SDL5 of the cell transistorM5 are also respectively connected with column lines L3, L4. Moreover,through selection of the word line WL0, while the simultaneouslyselected cell transistors M2, M3, M4 are conductive or produce a leakcurrent, there is a possibility that read-out of the cell transistor M1cannot be adequately performed. Consequently, in order to prevent such apossibility, column lines L3, L4 both assume a floating state.

Therefore, data which is read out through selection of word line WL0 isonly one stored data of cell transistor M1. When, with the selectsignals in an unchanged condition, 0V is applied to column line L1 and apredetermined voltage (1.6V) is applied to column line L2, it ispossible to read out another stored data of cell transistor M1. In anycase, actuation of select signals SEL1 to SEL4 only permits two-bit dataof a single cell transistor to be read-out.

Of the four associated cell transistors, the read-out of the remainingcell transistors M2, M3, M4 is the same, as shown in FIG. 5. In thiscase also, in response to selection of word line WL0, stored data of thecell transistors is read out one by one.

Since, in comparison with a widely used flash memory, a two-bitnon-volatile memory having a non-conductive trapping gate is capable ofstoring two-bit data, same is preferable as a large capacity memory. Onthe other hand, since, in the read-out operation thereof, according tothe data which is to be read out, the direction of the voltage appliedto the source-drain regions is reversed, as shown in FIGS. 4, 5, thereare problems in that the read-out circuit is complex and the read-outthroughput is poor.

DISCLOSURE OF THE INVENTION

Therefore, an object of the present invention is to provide a multiplebit non-volatile memory circuit in which the read-out throughput ishigh.

A further object of the present invention is to provide a multiple bitnon-volatile memory circuit, which, by means of the selection of oneword line, is capable of simultaneously reading out stored data of aplurality of cell transistors.

A further object of the present invention is to provide a multiple bitnon-volatile memory circuit which has a cell array structure capable ofhigh speed read-out.

In order to resolve the above-mentioned objects, one aspect of thepresent invention is a non-volatile memory circuit in which a pluralityof cell transistors having a non-conductive trapping gate are arranged,comprising: a plurality of source-drain lines, which are connectedcommonly with the source-drain regions of cell transistors adjacent inrow direction, wherein these adjacent source-drain lines are set to afloating state, a read-out voltage application state, a referencevoltage state, a read-out voltage state, and a floating state, and thesource-drain lines in the read-out voltage state is caused to functionas bit lines, such that a plurality of data are read out simultaneously.

According to a preferred embodiment of the present invention, by causinga group of source-drain lines of the above five states to besequentially shifted or moved, it is possible to read-out, athigh-speed, multiple bit data which has been recorded in celltransistors, and to therefore improve the read-out throughput.

In order to resolve the above-mentioned objects, another aspect of thepresent invention is a non-volatile memory circuit for recordingmultiple bit information comprising: a plurality of cell transistors,which have first and second source-drain regions formed at a substratesurface, and a first insulating layer, a non-conductive trapping gate, asecond insulating layer, and a control gate, formed sequentially on achannel region between the first and second source-drain regions,wherein cell transistors record data by trapping charge locally at atleast both ends of the trapping gate; a plurality of word lines, whichare connected with the respective control gate of the plurality of celltransistors arranged in a row direction; a plurality of source-drainlines, which are connected commonly with the source-drain regions of thecell transistors that are adjacent in the row direction; and a pluralityof page buffers, which are respectively connected with the plurality ofsource-drain lines, which supply, to each source-drain line within agroup of adjacent source-drain lines, a combination of a floating state,a read-out voltage state, a reference voltage state, a read-out voltagestate, and a floating state, in sequential order, and which read out therecorded data from the source-drain lines in the read-out voltage state.

Further, according to the preferred embodiment of the above invention,the plurality of page buffers shift, in a predetermined sequentialorder, the group of adjacent source-drain lines to which the combinationof states is supplied.

In this manner, it is possible to suitably read out all the multiple bitdata of the cell transistors.

Further, according to the preferred embodiment of the above invention,the plurality of page buffers output the read-out recorded data eachtime the combination of states is supplied to a first group of adjacentsource-drain lines which has, at both ends thereof, the source-drainlines of an odd number, and to a second group of adjacent source-drainlines which has, at both ends thereof, the source-drain lines of an evennumber.

By supplying the above combination of states to the first group ofadjacent source-drain lines and to the second group of adjacentsource-drain lines, recorded data in a group of eight adjacent celltransistors, for example, can be read out in eight bits to page buffers.At this stage, it is preferable that data in page buffers should besuitably outputted.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a figure that shows the constitution of a cell transistor of atwo-bit non-volatile memory.

FIG. 2 is a figure to illustrate programming, erasure and read-out of atwo-bit non-volatile memory.

FIG. 3 is a figure that shows states in which two-bit information isrecorded, of a two-bit non-volatile memory.

FIG. 4 is a figure that shows the constitution of a conventional memorycell array.

FIG. 5 is a chart that illustrates the operations of FIG. 4.

FIG. 6 is a figure that shows the constitution of the cell array of thepresent embodiment.

FIG. 7 is a chart that shows the voltage states of the source-drainlines during read-out.

FIG. 8 is a figure to illustrate the operations of the cell array duringread-out.

FIG. 9 is a circuit diagram of a page buffer in the present embodiment.

FIG. 10 is a timing chart of page buffer control signals.

PREFERRED EMBODIMENT OF THE INVENTION

The embodiment of the present invention will be described hereinbelow byreferring to the drawings. However, this embodiment does not limit thetechnological scope of the present invention.

The embodiment of the present invention is a non-volatile memory circuitwhich has a plurality of cell transistors capable of storing two bits.Cell transistors of this kind are the same as the conventional celltransistors illustrated by FIGS. 1, 2, 3. In other words, two-bitinformation can be recorded in a single cell transistor according towhether or not electrons are trapped at both ends of a non-conductivetrapping gate. For this reason, programming (write), erase and read-outoperations with respect to a cell transistor are as shown in FIG. 2, anda repeat description thereof is not provided here.

FIG. 6 is a figure to show the cell array constitution of the presentembodiment in which a plurality of such cell transistors are arranged ina matrix. In the cell array shown in FIG. 6, two word lines WL0, WL1 arearranged so as to extend in a row direction, and nine source-drain linesSDL1 to SDL9 are arranged so as to intersect with the word lines andextend in a column direction. The control gates of cell transistors M1to M9 are respectively connected with the word line WL0, and of the celltransistors M1 to M9, respectively, adjacent cell transistors areconnected commonly at the source-drain terminals, and source-drain linesSDL1 to SDL9 are connected commonly with these source-drain terminals.The respective control gates of cell transistors M11 to M19 aresimilarly connected with the word line WL1, and of these celltransistors also, adjacent cell transistors and are connected commonlyat the source-drain terminals, common source-drain lines SDL1 to SDL9being connected with these source-drain terminals. Consequently, thecontrol gates of all the cell transistors are connected with a word lineand the source-drain terminals are respectively connected withsource-drain lines.

Source and drain lines SDL1, SDL3 . . . SDL9 of an odd number arerespectively connected with page buffers P/B1, P/B3 . . . P/B9 arrangedon the upper side of FIG. 6. Further, source-drain lines SDL2, SDL4 . .. SDL8 of an even number are respectively connected with page buffersP/B2, P/B4 . . . P/B8 arranged on the lower side of FIG. 6. In responseto respective control signal groups STP, SBT, these page buffers set theconnected source-drain lines to a state that is any one of: a read-outvoltage state (BL) in which a read-out voltage is applied to afford afunction like that of a bit line, a reference voltage state (0V) inwhich a read-out reference voltage of 0V is applied; or a floating state(F).

When the connected source-drain lines of the cell transistors aresubjected to the read-out voltage state (BL) and the reference voltagestate (0V), the recorded data of the cell transistors is read out, viathe source-drain lines set to the read-out voltage state, by means ofthe page buffers connected with therewith. Furthermore, when any one ofthe connected source-drain lines is set to the floating state (F), acell transistor assumes a state in which no influence whatever isexerted on the read-out operation of adjacent cell transistor.

All of the page buffers set source-drain lines SDL connected thereto tothe above-mentioned read-out voltage state (BL) to read the record dataof cell transistors connected with these source-drain lines SDL, and tohold the data. In addition, the read-out data thus held may be output tooutput data bus PBout in response to a read-out control signal and aselect signal not shown in the figure.

In the cell array shown in FIG. 6, eight cell transistors are connectedwith respect to the word line WL0. As a result, through selection of theword line WL0, it is possible to read out recorded data totaling sixteenbits. However, since the eight cell transistors are provided with onlynine source-drain lines and nine page buffers, eight bits among theabove-mentioned sixteen bit recorded data are read out and held at atime. The held eight bit read-out data may be suitably outputted from anoutput bus PBout. Further, as described hereinbelow, when one word lineis selected, by means of control of each source-drain line, it ispossible to simultaneously read out four bit data to page buffers, andit is therefore possible to read out eight bit data bymeans of twocycles, and, in four cycles, it is possible to read out sixteen bit dataof eight cell transistors.

However, the number of cell transistors connected with one word line isnot limited to eight. Preferably, a plurality of cell transistor unitsUNIT1, UNIT2 are arranged in units of eight cell transistors. In thiscase, as shown in FIG. 6, a source-drain line SDL9, at a respective oneend of the adjacent cell transistor units UNIT1, UNIT2, is preferablyshared by same.

FIG. 7 is a chart to show source-drain line voltage states duringread-out. FIG. 8 is a figure to illustrate operation of the cell arrayduring read-out. With respect to the eight cell transistors, in each ofread-out cycles (1) to (4) shown in FIGS. 7 and 8, it is possible torespectively read out four bits at a time to the page buffers and,within four cycles, it is therefore possible to read out sixteen bitdata.

The read-out cycles (1) to (4) of FIG. 7 correspond to the read-outcycles (1) to (4) of FIG. 8. In the example here, as described above,eight bit data may be read out in the course of one page read. Further,each page read is constituted by two read-out cycles.

In the course of read-out cycle (1), the source-drain lines SDL1 to SDL9are set to the states SDL1 to SDL9=0V, BL, F, BL, 0V, BL, F, BL, 0V byrespective page buffers. Here, 0V signifies a reference voltage state,BL signifies a read-out voltage state, and F signifies a floating state,respectively. As a result, the existence of a current, as shown by anarrow in (1) of FIG. 8, is detected by page buffers P/B2, P/B4, P/B6,P/B8. In other words, in cell transistors M1, M4, M5, M8, data M1 (SD1),M4 (SD2), M5 (SD1), M8 (SD2), of the source-drain lines in a read-outvoltage state (BL), are read out and held by page buffers P/B2, P/B4,P/B6, P/B8. In the course of read-out cycle (1), as a result of thesource-drain lines of an even number being set to a read-out voltagestate, page buffers P/B2, P/B4, P/B6, P/B8 of an even number read outand hold recorded data of cell transistors corresponding thereto.

Next, in the course of read-out cycle (2), the source-drain lines SDL1to SDL9 are set to the states SDL1 to SDL9=BL, 0V, BL, F, BL, 0V, BL, F,F (or BL) by respective page buffers. As a result, the existence of acurrent, as shown by an arrow in (2) FIG. 8, is detected by page buffersP/B1, P/B3, P/B5, P/B7. In other words, in cell transistors M1, M2, M5,M6, data M1 (SD2), M2 (SD1), M5 (SD2), M6 (SD1), of the source-drainlines in a read-out voltage state, are read out and held by page buffersP/B1, P/B3, P/B5, P/B7. In the course of read-out cycle (2), as a resultof the source-drain lines of an odd number being set to a read-outvoltage state, page buffers P/B1, P/B3, P/B5, P/B7 of an odd number readout and hold recorded data of cell transistors corresponding thereto.

By means of read-out cycles (1), (2), recorded data corresponding to onepage constituted by a total of eight bits can be read out to and held ineight page buffers. In other words, a first page read is completed byread-out cycles (1), (2). Thereafter, through suitable selection of pagebuffers, the data thus held are outputted to an output data bus PBout.By providing a plurality of output data buses PBout, it becomes possibleto simultaneously output a plurality of data.

Next, a second page read operation is performed according torequirements. The second page read operation is performed by read-outcycles (3), (4). In the course of read-out cycle (3), the source-drainlines SDL1 to SDL9 are set to the states SDL1 to SDL9=F, BL, 0V, BL, F,BL, 0V, BL, F by respective page buffers. As a result, the existence ofa current, as shown by an arrow in (3) of FIG. 8, is detected by pagebuffers P/B2, P/B4, P/B6, P/B8. In other words, in cell transistors M2,M3, M6, M7, data M2 (SD2), M3 (SD1), M6 (SD2), M7 (SD1), of thesource-drain lines in a read-out voltage state, are read out and held bypage buffers P/B2, P/B4, P/B6, P/B8. In this manner, in the course ofread-out cycle (3), as a result of the source-drain lines of an evennumber being set to a read-out voltage state, page buffers P/B2, P/B4,P/B6, P/B8 of an even number read out and hold recorded data of celltransistors corresponding thereto.

Next, in the course of read-out cycle (4), the source-drain lines SDL1to SDL9 are set to the states SDL1 to SDL9=F (or BL), F, BL, 0V, BL, F,BL, 0V, BL by respective page buffers. As a result, the existence of acurrent, as shown by an arrow in (4) of FIG. 8, is detected by pagebuffers P/B1, P/B3, P/B5, P/B7. In other words, in cell transistors M3,M4, M7, M8, data M3 (SD2), M4 (SD1), M7 (SD2), M8 (SD1), of thesource-drain lines in a read-out voltage state, are read out and held bypage buffers P/B1, P/B3, P/B5, P/B7. In the course of read-out cycle(4), as a result of the source-drain lines of an odd number being set toa read-out voltage state, page buffers P/B1, P/B3, P/B5, P/B7 of an oddnumber read out and hold recorded data of cell transistors correspondingthereto.

By means of read-out cycles (3), (4), recorded data corresponding to onepage constituted by a total of eight bits can be read out to eight pagebuffers and, thereafter, are suitably outputted via an output bus PBout.

As described hereinabove, according to the present embodiment, when oneword line is selected, four bit data in eight cell transistors can besimultaneously read out to page buffers. As a result, in a case in whichN units of eight cell transistors are arranged, through selection of oneword line, it becomes possible to simultaneously read out 4N bit data topage buffers. As a result, by means of a cell array arrangementaffording a large capacity and through selection of one word line, it ispossible to simultaneously read out recorded data of a plurality of bitsto the page buffers.

Additionally, by means of four read-out cycles with respect to a unitconstituted from eight cell transistors, it is possible to read-outsixteen bit recorded data. Expressed differently, even in a caseinvolving the arrangement of a plurality of units constituted from eightcell transistors, while one word line is selected, bymeans of fourread-out cycles, it becomes possible to read out all recorded data tothe page buffers. Consequently, it is possible to improve the throughputof the read-out operation and shorten the read-out cycle.

It is understood that according to the above-described four kinds ofread-out cycle (1) to (4), a group of source-drain lines,which isconstituted from five adjacent source-drain lines set in the states F,BL, 0V, BL, F, is shifted to the right one by one. Since there are twosource-drain lines in a read-out voltage state in this group ofsource-drain lines, two-bit recorded data can read out simultaneously.

Further, with regard to the sequential order of the four kinds ofread-out cycle, other than the above-mentioned (1), (2), (3), (4), thefollowing sequential orders are permissible.

(1), (2), (4), (3);

(2), (1), (3), (4);

(2), (1), (4), (3);

(1), (4), (2), (3);

(1), (4), (3), (2);

(4), (1), (2), (3);

(4), (1), (3), (2),

In any of the cases, there is a requirement to combine read-out cyclesin which source-drain lines of an odd number or an even number are setto a read-out voltage state (BL). It may be understood from the abovevariations that, by suitably moving a group of source-drain linesconstituted from five adjacent source-drain lines set to the states F,BL, 0V, BL, F, it is possible to read out data of all the celltransistors.

Furthermore, here, “adjacent source-drain lines” means that source-drainlines, which are connected commonly with respect to cell transistorswhose source-drain regions are connected, are adjacent to one another.Therefore, for example, in a case in which every other cell transistorarranged in a matrix shape has a source-drain region thereof connected,according to the present embodiment, there is a requirement to shift thestates F, BL, 0V, BL, F with respect to five adjacent source-drain linesin a group of source-drain lines connected commonly with respect tostrings of cell transistors among which every other cell transistors areconnected.

FIG. 9 is a circuit diagram of a page buffer according to the presentembodiment. The page buffer shown in FIG. 9 has a function to set aconnected source-drain line SDLn to a read-out voltage state (BL), areference voltage state (0V), and a floating state (F), a sense ampfunction to read out recorded data of a cell transistor M via asource-drain line, and a latch function to hold this read-out data. Asshown in the upper portion in the figure, a transistor with an obliqueline indicates a p-channel transistor, and a transistor without anoblique line indicates an n-channel transistor.

The transistor N1 is conductive in response to a select signal YD1 andis a select gate that connects the page buffer circuit with the data busPBOUT. The transistor N6 is conductive in response to a load signal LDand is a gate that inputs write data from the data bus PBOUT. Further,transistors P2, P3, N4, N5 are an inverter circuit that amplifies andoutputs data held in the latch circuit constituted from inverters 10,12. This inverter circuit is activated when, in response to controlsignals LD, RD, transistors P3, N4 are conductive. As described above,the inverters 10, 12 are a latch circuit that temporarily holds writedata or read-out data.

Further, a sense amp circuit is constituted by a transistor P9, which isa constant current source in accordance with a bias control signalPBIAS, and transistors N10, N1. Also, transistor N12 is conductive tothus form a 0V reference voltage state. In addition, transistor N13 isconductive in response to a control signal BLCNTRL and thus connects thesource-drain line SDLn with a node SNS. Transistor N8 is conductiveduring programming and thus supplies a voltage, which corresponds todata to be programmed in the latch circuit, to the source-drain lineSDLn.

A combination of main control signals PBIAS, BLCNTRL, DIS, PGMON, whichare for setting source-drain lines to the read-out voltage state BL, thefloating state F, and the reference voltage state 0V, are shown in atable on the lower side of FIG. 9.

Next, a read-out operation of recorded data of cell transistors M, bymeans of the page buffer circuit, will be described.

First of all, it is assumed that the control signal LD is in an L level,RD is in an L level (or an H level is also acceptable), YD1 is in an Llevel (or an H level is also acceptable), SET is in an L level, PGMON isin an L level, PBIAS is in an H level, DIS is in an L level, and BLCNTRLis in an L level. Then, in the course of an initial step, by setting thecontrol signal DIS to an H level, and PGMON to an H level, transistorsN12 and N8 are conductive, node A is set to an L level, and node B to anH level.

In the course of the next step, setting the control signal PGMON to an Llevel makes the transistor N8 non-conductive, and setting the controlsignal BLCNTRL to an H level and PBIAS to an L level electricallyconnects the transistor P9, which is a constant current source, and thesource-drain line SDLn, which is connected with the cell transistor M.In this way, the source-drain line SDLn assumes a state in which aread-out voltage is applied, that is, a state that has a bit linefunction. At this time, 0V is applied as a reference voltage to thesource-drain line SDLn+1 on the opposite side of the cell transistor M.

Therefore, data stored by the cell transistor M can be determinedaccording to whether or not a current is caused to flow, within the celltransistor M, that is greater than the constant current (hereinaftertermed the sense current). A state in which the current flowing withinthe cell transistor M is greater than the sense current is termed a “1data storage state”, and a state in which the current flowing within thecell transistor M is less than the sense current is termed a “0 datastorage state.”

When the cell transistor M is in a “1 data storage state”, a node SNS isthen at an L level. Therefore, in the course of the next step, when an Hlevel pulse signal for the control signal SET is applied to thetransistor N11, since the transistor N10 is then not ON, an L levelstate for the node A and an H level state for the node B are maintained.Thereafter, when the control signal SET returns to an L level, the latchcircuit, which is constituted from the inverters 10, 12, and the sensecircuit are disconnected, and a 1 data state, for which the node A=Low,and the node B=High, is stored in the latch circuit portions 10, 12.

When the cell transistor M is in a “0 data storage state”, the node SNSis then at an H level in accordance with the sense current of theconstant current source transistor P9. Therefore, in the course of thenext step, when an H level pulse signal for the control signal SET isapplied to the transistor N11, since the detection transistor N10 isthen ON, inversion takes place such that the node A is in an H levelstate and the node B is in an L level state. Thereafter, when thecontrol signal SET returns to an L level, the latch circuit portions andthe sense circuit portions are disconnected, and a 0 data state, forwhich the node A=High, and the node B=Low, is stored in the latchcircuit portions 10, 12.

Next, in a case in which the page buffer P/Bn sets the source-drain lineSDLn to a floating state, the control signal BLCNTRL may be either at anH level or an L level, but setting the control signal PBIAS to an Hlevel makes the transistor P9 non-conductive and setting the controlsignal PGMON to an L level makes the transistor N8 non-conductive, andthe control signal DIS is set at an L level. As a result, thesource-drain line SDLn assumes a floating state. In this manner, a celltransistor connected with this source-drain line exerts no influencewhatever on the read-out operation of adjacent cell transistor.

Further, in a case in which the page buffer P/Bn sets the source-drainline SDLn to a reference voltage state, the control signal DIS is set toan H level such that the transistor N12 is made conductive, and thecontrol signal BLCNTRL is set to an H level such that the transistor N13is made conductive, such that 0V is applied to the source-drain lineSDLn via the transistors N12, N13.

FIG. 10 is a timing chart for page buffer control signals in two pageread operations constituted from four read-out cycles shown in FIGS. 7,8. As shown in FIG. 10, the first page read is performed by means offormer half and latter half read-out cycles (1), (2), but, beforehand, aset operation in the page buffer is performed, and, thereafter,according to requirements, an output operation to a data bus PBout maybe performed. The set operation and the output operation are asdescribed hereinabove. Further, the second page read is the same.Moreover, a reference number TP (top) is respectively assigned tocontrol signals STP for page buffers of an odd number in FIGS. 6 and 8,and a reference number BT (bottom) is respectively assigned to controlsignals SBT for page buffers of an even number in FIGS. 6 and 8.

First of all, in the course of the initial read-out cycle (1) of a firstpage, control signals PBIAS_BT_0 and PBIAS_BT_1 for page buffers of aneven number are set to a given bias level (L level), the control signalsDIS_BT_0 and DIS_BT_1 are both set to an L level, and the control signalBLCNTRL_BT is set to an H level. In this manner, a read-out voltage isapplied to source-drain lines SDL2, SDL4, SDL6, SDL8 of an even number,and these source-drain lines thus function as bit lines.

On the other hand, control signals PBIAS_TP_0 and PBIAS_TP_1 for pagebuffers of an odd number are set to an H level, the control signalDIS_TP_0 is set to an H level, DIS_TP_1 is set to an L level, and thecontrol signal BLCNTRL_TP is set to an H level. In this manner, amongthe source-drain lines of an odd number, 0V is applied to SDL1, SDL5,SDL9 such that same assume a reference voltage state, and SDL3, SDL7assume a floating state.

In the mean time, the word line WL is set at an H level, and, as per theabove-described sense operation, the data stored by the cell transistorsM is determined. Next, by applying an H level pulse signal for thecontrol signal SET_BT, data is determined and is stored in the latchcircuit portions 10, 12 of the page buffer P/Bn.

Next, in the course of the second read-out cycle (2) of a first page,control signals PBIAS_TP_0 and PBIAS_TP_1 for page buffers of an oddnumber are set to a given bias level (L level), the control signalsDIS_TP_0 and DIS_TP_1 are set to an L level, and the control signalBLCNTRL_TP=High. In this manner, a read-out voltage is applied tosource-drain lines SDL1, SDL3, SDL5, SDL7, SDL9 of an odd number, andthese source-drain lines thus function as bit lines.

In the course of an actual operation, the data which is stored in thepage buffer connected with the source-drain line SDL9 is not employedsince such data is garbage data. As a result, the source-drain line SDL9may also be set to a floating state. However, in a case in which eightor more cell transistors are arranged in a row direction, thesource-drain line SDL9 is desirably made to function as a bit line.

On the other hand, control signals PBIAS_BT_0 and PBIAS_BT_1 for pagebuffers of an even number are set to an H level, the control signalDIS_BT_0 is set to an H level, DIS_BT_1 is set to an L level, and thecontrol signal BLCNTRL_BT is set to an H level. In this manner, amongthe source-drain lines of an even number, 0V is applied to SDL2, SDL6,such that same assume a reference voltage state, and SDL4, SDL8 assume afloating state.

In the mean time, the word line WL is set at an H level and the datastored by the cell transistors is thus determined. Next, by supplying anH level pulse signal for the control signal SET_TP to the transistorN11, data is determined and is stored in the latch circuit portions of apage buffer.

In the course of the above two read-out cycles, data of the first page(of eight bits here) is latched in eight upper and lower page buffers.Thereafter, by setting the page buffer selection signal YD1 to an Hlevel, for example, data thus latched is outputted to an output busPBout.

As described above, according to requirements, following externalread-out of first page data from the page buffers, if necessary, anoperation commences to read out data of a second page. The read-out ofdata of a second page will now be described with a little detail.

First of all, in the course of the first read-out cycle (3) of a secondpage, control signals PBIAS_BT_0 and PBIAS_BT_1 for page buffers of aneven number are set to a given bias level, the control signals DIS_BT_0and DIS_BT_1 are set to an L level, and the control signal BLCNTRL_BT isset to an H level. In this manner, a read-out voltage is applied tosource-drain lines SDL2, SDL4, SDL6, SDL8 of an even number, and thesesource-drain lines thus function as bit lines.

On the other hand, control signals PBIAS_TP_0 and PBIAS_TP_1 for pagebuffers of an odd number are set to an H level, the control signalDIS_TP_0 is set to an L level, DIS_TP_1 is set to an H level, and thecontrol signal BLCNTRL_TP is set to an H level. In this manner, amongthe source-drain lines of an odd number, 0V is applied to SDL3, SDL7,and SDL1, SDL5, SDL9 assume a floating state. In the mean time, the wordline is set to an H level and data stored by the cell transistors M isthus determined and held in the latch circuit portions.

Next, in the course of the second read-out cycle (4) of a second page,control signals PBIAS_TP_0 and PBIAS_TP_1 for page buffers of an oddnumber are set to a given bias level, the control signals DIS_TP_0 andDIS_TP_1 are set to an L level, and the control signal BLCNTRL_TP is setto an H level. Therefore, source-drain lines SDL1, SDL3, SDL5, SDL7,SDL9 of an odd number function as bit lines. However, in the course ofan actual operation, the data which is stored in the page bufferconnected with the source-drain line SDL1 is not employed since suchdata is garbage data. As a result, the source-drain line SDL1 may alsobe set to a floating state. However, on the grounds that this operationis the same as the case of the read-out cycle (2), the source-drain lineSDL1 is desirably utilized as a bit line.

On the other hand, control signals PBIAS_BT_0 and PBIAS_BT_1 for pagebuffers of an even number are set to an H level such that the transistorN9 is non-conductive, the control signal DIS_BT_0 is set to an L level,DIS_BT_1 is set to an H level, and the control signal BLCNTRL_BT is setto an H level. In this manner, a reference voltage 0V is applied to thesource-drain lines SDL4 and SDL8, and source-drain lines SDL2 and SDL6assume a floating state. In this state, the word line is set at an Hlevel, and data stored by the cell transistors M is [thus] determinedand stored in the latch circuit portions.

Thereafter, eight-bit data latched in the course of the second page readmay be suitably outputted to an output data bus PBout.

According to the above-described embodiment, an example was described inwhich eight cell transistors were connected in an adjacent manner to oneword line. However, the present invention is not limited to such anumber of cell transistors. Indeed, also in a case in which a greaternumber of cell transistors is connected with one word line, duringactuation of the word line to an H level, in the course of one read-outcycle, it is possible to simultaneously read out data of a plurality ofbits to the page buffers. Moreover, in the course of a plurality ofread-out cycles, it is possible to read out all data. In such a case,with regard to the states of the adjacent source-drain lines, acombination F, BL, 0V, BL, F shifts for each read-out cycle, or theadjacent source-drain lines are controlled to permit the shift. Bysetting these five states for the source-drain lines, it is possible tosimultaneously read out two-bit data from within units constituted fromfour cell transistors. To adjoin means, as described hereinabove,adjacent with respect to source-drain lines possessed by strings of celltransistors whose source-drain regions are mutually connected.

The scope of protection of the present invention hereinabove is notlimited to the above-described embodiment but rather also covers theinventions appearing in the patent claims and equivalent items thereof.

INDUSTRIAL UTILITY

By means of the present invention hereinabove, a non-volatile memorycircuit, which comprises cell transistors having a non-conductivetrapping gate, is capable of simultaneously reading out a plurality ofdata in the course of one read-out operation and is therefore capable ofimproving read-out throughput.

What is claimed is:
 1. Non-volatile memory circuit for recordingmultiple bit information, comprising: a plurality of cell transistors,which have first and second source-drain regions formed at a substratesurface, and a first insulating layer, a non-conductive trapping gate, asecond insulating layer, and a control gate, formed sequentially on achannel region between the first and second source-drain regions,wherein cell transistors record data by trapping charge locally at atleast both ends of said trapping gate; a plurality of word lines, whichare connected with the respective control gates of said plurality ofcell transistors arranged in a row direction; a plurality ofsource-drain lines, which are connected commonly with the source-drainregions of said cell transistors that are adjacent in said rowdirection; and a plurality of page buffers, which are respectivelyconnected with said plurality of source-drain lines, which supply, toeach source-drain line within a group of adjacent source-drain lines, acombination of a floating state, a read-out voltage state, a referencevoltage state, a read-out voltage state, and a floating state, insequential order, and which read out said recorded data from thesource-drain lines in said read-out voltage state.
 2. The non-volatilememory circuit according to claim 1, wherein said plurality of pagebuffers shift, in a predetermined sequential order, said group ofadjacent source-drain lines to which said combination of states issupplied.
 3. The non-volatile memory circuit according to claim 1,wherein said plurality of page buffers output said read-out recordeddata each time said combination of states is supplied to a first groupof adjacent source-drain lines which has, at both ends thereof, saidsource-drain lines of an odd number, and to a second group of adjacentsource-drain lines which has, at both ends thereof, said source-drainlines of an even number.
 4. The non-volatile memory circuit according toclaim 1, wherein said plurality of page buffers shift said combinationof states in a predetermined sequential order with respect to a celltransistor unit which has eight cell transistors respectively connectedbetween nine adjacent source-drain lines, and, each time a shift isperformed, holds read-out recorded data four bits at a time.
 5. Thenon-volatile memory circuit according to claim 4, wherein said pluralityof page buffers output said held eight bit recorded data, each time saidcombination of states is supplied to a first group of adjacentsource-drain lines which has, at both ends thereof, said source-drainlines of an odd number, and to a second group of adjacent source-drainlines which has, at both ends thereof, said source-drain lines of aneven number.
 6. The non-volatile memory circuit according to claim 4 or5, wherein a plurality of said cell transistor units are provided. 7.The non-volatile memory circuit according to claim 6, wherein asource-drain line of one end of said transistor cell unit is common alsoto a source-drain line of one end of an adjacent transistor cell unit.